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The file carried gl's base measurement (7c6f6886, before pa and mv landed) and said so rather than
hiding it. The merge discharged that note exactly as written, and the two-sided ratchet named both
deltas by itself rather than being told:
- GetProgramForDraw@DrawArrays no longer appears - pa retired it, 62 entries to 0, and it was the
read that fired once per draw and kept every draw barriered. Removed here, in the wave that
retired it, which is the whole point of the other side of the ratchet: an expected set that keeps
rows nothing writes any more is how a lane rots green.
- GetBufferBindingSlot@DrawArrays is new, 18 entries, all of them the two indirect multi-draw
tiers. mv NAMED it as a latent row before it could fire - BoundDrawIndirectBufferId's
GetBufferBindingSlot(DrawIndirect), which "would surface as GetBufferBindingSlot@DrawArrays if an
indirect tier were ever forced under strict" - and then gated the five tiers, which forced it.
It retires in P8 (FieldOwnership.def:78), so it is a debt owed by a later phase and not by this
one. Added with that reason.
Measured on the integration tree, two independent instruments agreeing (Harness/split_log_paths.py
markers, and a separate per-entry census that drives each entry's own command and ENVIRONMENT from
ctest --show-only=json-v1):
integration-split 181 / 181 green
Fatal{UnmigratedPipeInput 0 distinct pairs
Admitted{ 10 distinct pairs - 8 by the generated table, 2 by escalation
So "the strict lane is hard green" is now a statement a script evaluates, not one a reader argues:
every entry completes, no Fatal marker over the log set ctest itself declares, every Admitted marker
checked against the same table the C++ answers from, and the ratchet fails in BOTH directions.
Gate on this head: build rc=0, unit 2254/2254, integration-split 181/181, integration-gpu 1359/1359,
gens all rc=0, flavours rc=0 (pull 915 TUs push-absent, push 929 TUs push=1).