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[Test] (P8-SV): WireMipShapeScenario (3D chain on both backends x every arm, 1D depth decline on Magma split+spawn, the 3D chain under the validation layer inproc) and WireIndirectDispatchScenario (both backends x every arm, Magma gated .IndirectDispatch.), the MipmapDepthStencilAspect tally in F1's depth/stencil decline case, WireDeclinePeek, and the two parity rows
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2026-09-30 03:44:03 -04:00 |
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[Merge] (P8): integrate package E - a texture readback the Espryt driver refuses is answered from the split server's staged store, which now follows glCopyImageSubData (FollowCopy, client-box merge, sticky driver-written mark, named decline texture-readback-store-declined); CopyImageStoreReadbackScenario on both backends x every arm plus the extent-scoped StoreRead knob; the dead CopyImageSubData+RENDERBUFFER latch goes (census 79 -> 78)
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2026-09-30 02:17:51 -04:00 |
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[Merge] (P8): integrate package D - the Magma wire arm issues glDraw*Indirect / glMultiDraw*Indirect[Count] natively from the wire store (vkCmdDraw*Indirect[Count]) instead of a CPU expansion behind a GPU-idle wait, with an INDIRECT_COMMAND_READ barrier once per shader write; windr[] PipeStats counters and WireIndirectDrawScenario on both backends x every arm
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2026-09-30 01:28:20 -04:00 |
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[Merge] (P8): integrate package C - the Espryt split server refreshes its staged copy of a buffer a shader wrote before a CPU reader consumes it (storage/atomic/buffer-image marks, XFB captures into the copy; restart rewrite, multi-draw rebase, *IndirectCount, CPU-fed indirect fields, XFB scatter and fp64 narrowing read through SplitHostBytesForCpuRead); GpuWrittenDrawInputScenario (12 cases) on the Espryt split arms
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2026-09-30 00:45:16 -04:00 |
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[Merge] (P8): integrate package B - Espryt glGenerateMipmap on the server: the record's generated window (BASE/MAX clip, B1) and RGB16F/RGB32F natively or on the server's CPU from the driver's level (B2), retiring both split generate-mipmap names; GenerateMipmapServerScenario on both backends x monolith/Split/Spawn/Tcp plus the forced-CPU arm
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2026-09-30 00:01:29 -04:00 |
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[Merge] (P8): integrate package A - register the monolith-only cases on split/spawn/tcp (P8Coverage.cmake, five server-knob tcp supervisors), gate them with split_coverage.py and its exemption table, pin the tcp supervisor's Vulkan env
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2026-09-29 23:37:12 -04:00 |
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[Docs] (P8-A): the note says what the census measured about the audit's 396 and DoublePrecision on tcp, and the knob-port comment names the split/verify one-port overlap
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2026-09-29 23:18:08 -04:00 |
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[Fix] (Espryt, P8-E): a texture readback the driver refuses is answered from the server's staged store, which now follows glCopyImageSubData (FollowCopy, client-box merge, sticky driver-written mark, named decline); CopyImageStoreReadbackScenario on both backends x four arms plus the extent-scoped store-read knob; the dead CopyImageSubData+RENDERBUFFER latch goes (census 79 -> 78)
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2026-09-29 22:43:02 -04:00 |
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[Fix] (Espryt, P8-C): the split server refreshes its staged copy of a buffer a shader wrote before a CPU reader consumes it - storage/atomic/buffer-image writes mark the server twin, XFB captures land in the copy, the restart rewrite, multi-draw rebase, *IndirectCount, CPU-fed indirect fields, XFB scatter and fp64 narrowing read through SplitHostBytesForCpuRead; GpuWrittenDrawInputScenario (12 cases) on the split arms
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2026-09-29 22:38:33 -04:00 |
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[Test] (P8-F): give the mip shader-shape decline its own .ShaderMipDecline. tail - spawn_lane_parity.py holds each server-knob tail to exactly one case, and sharing .ShaderMip1. named two
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2026-09-29 22:37:49 -04:00 |
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[Perf] (P8-D, Magma): the wire arm issues glDraw*Indirect / glMultiDraw*Indirect[Count] as vkCmdDraw*Indirect[Count] from the wire store instead of expanding them on the CPU behind a GPU-idle wait (create-indirect split: 321 waits / ~8 s -> 0), with an INDIRECT_COMMAND_READ barrier once per shader write; windr[] PipeStats counters, WireIndirectDrawScenario on both backends x every arm, notes/p8/D.md
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2026-09-29 22:32:49 -04:00 |
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[Fix] (P8-A): the tcp lane's shared supervisor carries the Vulkan ICD and the three lavapipe iterationRP repairs, which Magma reads in the server - DirectVulkan.Tcp IterationRPProgram203 missed its golden output by one texel without them
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2026-09-29 22:30:20 -04:00 |
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[Fix] (Espryt, P8-B): glGenerateMipmap on the server - the record's plan is the generated window (B1) and RGB16F/RGB32F generate natively or on the server's CPU from its own level (B2), retiring both split generate-mipmap names; GenerateMipmapServerScenario on both backends x monolith/Split/Spawn/Tcp plus the forced-CPU arm
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2026-09-29 22:22:55 -04:00 |
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[Refactor] (P8-F): reclassify what our client cannot send - the multi-draw client-indices/instanced latches and Magma's client-vertex-array become ProtocolCorruption, Magma's mipmap-shader-format-or-shape becomes a named decline decided before the chain grows (with a knob-forced 3D case on split and spawn), and the three unpublished cap bits and the index-mirror sentinel are marked reserved
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2026-09-29 22:15:29 -04:00 |
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[Test] (P8-A): register the monolith-only integration cases on the split, spawn and tcp arms (P8Coverage.cmake: 246 ambient cases, five server-knob lanes each on its own tcp supervisor), retire the ClientSideIndices and GuiBatch exclusions, and gate the rest with split_coverage.py and its exemption table
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2026-09-29 22:14:31 -04:00 |
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[Test] (P11 B2): DeletedBoundBufferScenario - a buffer deleted while bound to a storage, uniform, atomic-counter or transform-feedback point, its slot reused, then a dispatch and a draw, on monolith and Split/Spawn/Tcp for both backends; and the one-process arena pair as a regression
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2026-09-29 19:32:19 -04:00 |
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[Test] (P11 B2): pin MOBILEGL_ITEST_REQUIRE_GPU=1 on every Espryt split/spawn itest environment, as the Magma and Espryt TCP lists do - a handshake-time Fatal fails there instead of skipping as a ctest pass
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2026-09-29 18:57:04 -04:00 |
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[Test] (P11 B2): LargeArenaAdoptionScenario - a draw still queued when the arena is rewritten or respecified keeps the bytes it was issued against (no readback between the two draws, so an in-place write or an early free shows)
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2026-09-29 18:06:48 -04:00 |
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[Test] (P11 B2): T0 protocol on the host - the Offer inbox (late, out of order, stale, missing) over both aux channels, the whole T0 path on a stand-in platform, A1's two handshake-Fatal cases rewritten as named fallbacks, revision 4 refused by name, AdoptTier0 lanes on the shared-segment arms and the allow switch through spawn
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2026-09-29 17:50:50 -04:00 |
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[Test] (P11 M2): DescriptorPoolGrowthScenario waits for the inproc server to apply every record it emitted before each census read - under run-ahead a census right after the burst's swap read the pools before the burst, or a trim a frame late
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2026-09-29 13:29:38 -04:00 |
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[Test] (P11 M2): dev's two Magma scenarios on the split arms - both on Espryt's three arms, OversizedRecordingSplitScenario on Magma's three (and pinned to a 64-draw budget on split and spawn, where the server reads it), DescriptorPoolGrowthScenario's census cases on Magma's split arm only; the split-recording arming reads both role logs and dev's pinned lane holds its log's RESOURCE_LOCK, and the census cases count the sets the wire arm holds between its descriptor rewinds
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2026-09-29 12:20:15 -04:00 |
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[Merge] (P11): dev@c14283ee - scattered sub-image writes upload exactly their texels, Magma submits a frame's recording every 16384 draws with backpressure, and Magma grows descriptor pools geometrically and trims a quiet slot whole; the handle arm notes driver-side writes by handle and the wire arm splits recordings and keeps the trim's epoch peak across descriptor rewinds
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2026-09-29 12:11:37 -04:00 |
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[Test] (Magma): descriptor pool growth and trim - the pure sizing policy adds O(log N) pools for an N-set frame, and DescriptorPoolGrowthScenario's 4096-distinct-set frame lands whole on both backends, grows at most 7 pools, and is given back after quiet frames and re-grown while they are still in flight
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2026-09-29 10:34:16 -04:00 |
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[Test] (Magma): OversizedRecordingSplitScenario carries state across the split - a depth occluder, a stencil mark, an additive blend destination, a 4x multisample target resolved after it, occlusion and primitives-generated queries and a transform-feedback capture left open across it, each checked on both backends and in the budget-64 lane
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2026-09-29 09:44:58 -04:00 |
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[Test] (Magma): OversizedRecordingSplitScenario - a 1024-draw frame, one pixel and one uniform value per draw, lands whole on both backends; the DirectVulkan.SplitRecording lane pins the draw budget to 64 and asserts the split fired
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2026-09-29 09:44:58 -04:00 |
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[Test] (MG_IntegrationTest, MG_Test): scattered writes over a GPU clear on both backends - two distant 2x2 boxes, a hundred boxes, boxes filling 3/4 of their union and three quadrants spanning the level, the 3/4 and level-spanning cases again at the image-bindable re-mint, and a MipmapStorage footprint fuzz against a reference bitmap
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2026-09-29 09:06:07 -04:00 |
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[Test] (P11 A1/A2): LargeArenaAdoptionScenario asserts the tier its arena landed in and reads the tcp AdoptTier0 refusal; registered on Split/Spawn/Tcp for both backends (Espryt through the split-arms macro, Magma's Arena. block and Buffers lane), the monolith lanes declare adopted
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2026-09-29 07:23:41 -04:00 |
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[Fix] (P11 A1): settle MOBILEGL_IPC_ADOPT_TIER at the handshake from the data plane - a stream refuses T0/T1 by name and runs T2 on either side, a client over shared segments dies by name before any record, the at-use check trusts the settlement; unit gates on a real tcp session and a real inproc handshake
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2026-09-29 07:23:41 -04:00 |
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[Test] (P11 M): ImageBindableRemintScenario pins a barrier before its imageLoad copy - the kept-allocation case read the pre-clear upload once on push-monolith under load, the ID-P9-11 shape
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2026-09-29 06:47:11 -04:00 |
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[Test] (P11 M): P4aFinalFixScenario expects no re-mint count on the monolith arm either - dev's 568090f0 keeps an immutable, unwidened allocation there as the server already did
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2026-09-29 06:47:10 -04:00 |
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[Test] (P11 M): dev's ImageBindableRemint and PartialUploadOverGpuContent scenarios on the Split/Spawn/Tcp arms of both backends, three scattered-upload cases for the handle arm's carried layout, and TextureRemintPullScenario's monolith Espryt skip retired
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2026-09-29 06:30:54 -04:00 |
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[Merge] (P11): dev@c60639db - the Espryt image-bindable re-mint reads GPU levels back on the monolith arm too, partial writes into converted or reshaped levels upload only their region on every arm, Magma orders an upload after the recording's writes and queued clears, and Magma's eglSwapInterval reaches the swapchain
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2026-09-29 06:15:56 -04:00 |
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[Test] (P10): the fence bench comment - the replay corpus does carry timed fence waits (improved-transparency-minecraft-26.3), the bench isolates the shape
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2026-09-29 05:29:00 -04:00 |
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[Test] (P10 B): AsyncCompileScenario (AsyncOn/AsyncOff/OptimisticShaderStatus), XfbPrimitiveQueryScenario and PrimitivesGeneratedNoXfbScenario on the split arms of both backends - Espryt Split/Spawn/Tcp, Magma Split/Spawn/Tcp gated, PrimGenReroute split+spawn only
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2026-09-29 04:34:02 -04:00 |
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[Test] (P10 A): PacedFrameFenceWaitsBench - the per-frame timed wait on an older frame's fence as an opt-in measurement (MGITEST_FENCE_PACE_BENCH, _LAG) on both backends
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2026-09-29 04:29:49 -04:00 |
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[Fix] (Magma): an upload into an image the open recording already wrote, or that still has a queued clear, is submitted after that work - a glTexSubImage after a clear or a draw into the level no longer ends up under it
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2026-09-29 04:28:55 -04:00 |
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[Feat] (MG_Remote): fence polls are answered from the server's reports - the apply thread posts kEventFenceSignaled as the GPU finishes each client fence (and submits and re-checks while idle), glClientWaitSync(0) / glGetSynciv answer locally, and only every MOBILEGL_IPC_POLL_ESCALATE-th unanswered poll crosses
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2026-09-29 03:59:44 -04:00 |
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[Test] (P9 W2): TextureRemintPullScenario - fourteen re-mint cases on both backends x monolith/Split/Spawn/Tcp, and the forced-readback-failure fallback entries
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2026-09-29 03:23:54 -04:00 |
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[Fix] (Espryt): the image-bindable re-mint reads every level back from the driver texture before replaying it, so GPU-written levels survive the first glBindImageTexture - iris-derivative SSIM 0.996196552 -> 0.996376198
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2026-09-29 03:06:45 -04:00 |
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[Feat] (MG_Remote): a read into a pixel pack buffer crosses as read_pixels_to_buffer / get_texture_image_to_buffer and waits for nothing - the server lands the rows through the buffer-write gate on both backends, the client marks the buffer GPU-written, and a device lost with the write still owed ends in Fatal{ReadbackDeclined, "buffer-writeback"}
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2026-09-29 02:02:29 -04:00 |
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[Test] (MG_IntegrationTest/Scenarios): The P4a white-box applier reads fence on a readback.
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2026-09-26 12:53:10 +08:00 |
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[Test] (MG_IntegrationTest/Scenarios): Fence the object-death gates on a readback instead of a clear.
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2026-09-26 09:36:37 +08:00 |
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[MG_Remote, MG_Test, MG_IntegrationTest, scripts] (P7): a spawned server reports SurfaceProgress while its apply thread runs a surface op, so the client's reply budget bounds silence and a cold bring-up past 20 s is waited for
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2026-09-23 18:17:02 -04:00 |
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[MG_Backend, MG_Test, MG_IntegrationTest, scripts] (P7): a private image placeholder is keyed by (shape, unit) and capped, and the depth-resolve identity is built by a tested helper
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2026-09-23 17:45:57 -04:00 |
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[MG_Backend, MG_IntegrationTest, scripts] (P7): an invalid or empty image unit on the wire arm binds a null storage descriptor (VK_EXT_robustness2 nullDescriptor), else a placeholder private to its (binding, unit)
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2026-09-23 17:04:13 -04:00 |
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[MG_Backend, MG_IntegrationTest] (P7): a real-probe negative control proves the depth-resolve measurement can see a broken render-pass arm on the host
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2026-09-23 15:20:17 -04:00 |
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[MG_Backend, MG_Test, MG_IntegrationTest, scripts] (P7): choose the multisample depth/stencil resolve arm by a device probe with a shader-arm control instead of the Qualcomm vendor id
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2026-09-23 15:13:44 -04:00 |
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[MG_Backend, MG_IntegrationTest, scripts] (P7): pin the Qualcomm depth/stencil resolve arm order on the split and spawn arms
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2026-09-23 15:13:44 -04:00 |
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[MG_Backend, MG_IntegrationTest] (P7): copy 1:1 single-sample depth/stencil blits on the Magma wire arm
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2026-09-23 15:13:44 -04:00 |
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[MG_IntegrationTest] (P7): the texture-view window case joins the gated image-unit arms
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2026-09-23 14:39:35 -04:00 |
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