MobileGL

BufferArena.cpp

[MG_Backend] (Disaggregated): consume Magma application buffers from server resources

2026-09-20 02:37:02 -04:00

BufferArena.h

[Feat] (MG_Backend/DirectVulkan): Buffer arena, buffer slice

2026-03-19 17:23:52 +08:00

BufferSlice.h

[Feat] (MG_Backend/DirectVulkan): Buffer arena, buffer slice

2026-03-19 17:23:52 +08:00

FrameContext.cpp

[MG_Backend, MG_Remote] (P7): draft B4 aggregate waits and staged extent reset

2026-09-23 03:53:37 -04:00

FrameContext.h

[Feat] (DirectVulkan): pre-pass command stream for reorderable out-of-pass work

2026-07-30 02:43:13 -04:00

MagmaPipeArms.h

[MG_Backend, MG_State, MG_Pipe, MG_Remote, MG_Impl, MG_IntegrationTest, docs] (P7): magma installs a state-object death table, and the inproc arm stops losing every object_death

2026-09-22 16:07:13 -04:00

MagmaProgramSource.h

[MG_State, MG_Backend, MG_Test, docs] (P7): the reflection archive publishes the storage-block index space, and both magma consumers read it

2026-09-22 16:07:59 -04:00

PipelineFactory.cpp

[Magma] key wire pipelines by exact render-pass compatibility identities

2026-09-20 08:42:47 -04:00

PipelineFactory.h

[Magma] key wire pipelines by exact render-pass compatibility identities

2026-09-20 08:42:47 -04:00

ProgramFactory.cpp

[MG_Backend] (Disaggregated): make Magma descriptors and present barriers Vulkan-valid

2026-09-20 05:17:21 -04:00

ProgramFactory.h

[MG_Backend] (Disaggregated): P5f fm - build Magma programs from server archive views

2026-09-19 22:26:23 -04:00

SubmitFencePrefix.h

[MG_Backend, MG_Test] (P7): prove aggregate waits with a single-fence control

2026-09-23 03:53:37 -04:00

SwapchainObject.cpp

[Merge] (P11): dev@c60639db - the Espryt image-bindable re-mint reads GPU levels back on the monolith arm too, partial writes into converted or reshaped levels upload only their region on every arm, Magma orders an upload after the recording's writes and queued clears, and Magma's eglSwapInterval reaches the swapchain

2026-09-29 06:15:56 -04:00

SwapchainObject.h

[Fix] (Magma): eglSwapInterval reaches the swapchain - 0 picks IMMEDIATE, else MAILBOX, else FIFO; >= 1 FIFO; < 0 FIFO_RELAXED, else FIFO; rebuilt after the next present when the mode changes (MC 26.3 vsync on: 190-290 fps -> 120)

2026-09-29 05:51:18 -04:00

UniformManager.cpp

[Fix] (Magma): a uniform block declared at an empty binding point reads a zeroed block on the monolith arm instead of dereferencing a null buffer, as the wire arm already does

2026-09-29 19:32:19 -04:00

UniformManager.h

[Merge] (P11): dev@c14283ee - scattered sub-image writes upload exactly their texels, Magma submits a frame's recording every 16384 draws with backpressure, and Magma grows descriptor pools geometrically and trims a quiet slot whole; the handle arm notes driver-side writes by handle and the wire arm splits recordings and keeps the trim's epoch peak across descriptor rewinds

2026-09-29 12:11:37 -04:00

VertexInputStateBuilder.cpp

[Feat] (MG_Backend/DirectVulkan): vertex input state factory

2026-02-17 10:24:01 +08:00

VertexInputStateBuilder.h

[Feat] (MG_Backend/DirectVulkan): vertex input state factory

2026-02-17 10:24:01 +08:00

VertexInputStateFactory.cpp

[MG_Backend, MG_IntegrationTest, docs] (P7): the magma vertex-layout refusal splits into one protocol fatal and seven masked attributes

2026-09-22 16:07:59 -04:00

VertexInputStateFactory.h

[MG_Backend] (Disaggregated): memoize immutable wire vertex format capabilities

2026-09-20 08:21:24 -04:00

VkBufferManager.cpp

[Perf] (P8-D, Magma): the wire arm issues glDraw*Indirect / glMultiDraw*Indirect[Count] as vkCmdDraw*Indirect[Count] from the wire store instead of expanding them on the CPU behind a GPU-idle wait (create-indirect split: 321 waits / ~8 s -> 0), with an INDIRECT_COMMAND_READ barrier once per shader write; windr[] PipeStats counters, WireIndirectDrawScenario on both backends x every arm, notes/p8/D.md

2026-09-29 22:32:49 -04:00

VkBufferManager.h

[Perf] (P8-D, Magma): the wire arm issues glDraw*Indirect / glMultiDraw*Indirect[Count] as vkCmdDraw*Indirect[Count] from the wire store instead of expanding them on the CPU behind a GPU-idle wait (create-indirect split: 321 waits / ~8 s -> 0), with an INDIRECT_COMMAND_READ barrier once per shader write; windr[] PipeStats counters, WireIndirectDrawScenario on both backends x every arm, notes/p8/D.md

2026-09-29 22:32:49 -04:00

VkBufferObject.cpp

[Feat] (Magma, P11 B2): import a T0 store through VK_ANDROID_external_memory_android_hardware_buffer as a wire buffer (external VkBufferObject), serial-gated release, done-no-bytes readback, and the sustained-lock POST on the renderer's device

2026-09-29 17:50:50 -04:00

VkBufferObject.h

[Feat] (Magma, P11 B2): import a T0 store through VK_ANDROID_external_memory_android_hardware_buffer as a wire buffer (external VkBufferObject), serial-gated release, done-no-bytes readback, and the sustained-lock POST on the renderer's device

2026-09-29 17:50:50 -04:00

VkClearManager.cpp

[Refactor] (Magma): route every frontend read through MGB_CTX - 164 arrow sites sed'd, 49 non-arrow lines converted (43 asserts keep their meaning as MGB_CTX_LIVE); pull build byte-identical

2026-09-06 04:41:28 -04:00

VkClearManager.h

[Feature, Fix, Test] (GLState, GLImpl, DirectVulkan, DirectGLES): implement glTextureView over shared texture storage

2026-08-22 10:41:52 -04:00

VkRenderPassManager.cpp

[Refactor] (Magma): route every frontend read through MGB_CTX - 164 arrow sites sed'd, 49 non-arrow lines converted (43 asserts keep their meaning as MGB_CTX_LIVE); pull build byte-identical

2026-09-06 04:41:28 -04:00

VkRenderPassManager.h

[Fix] (DirectVulkan): legal view types for layered 3D/cube attachments, and a real failure channel for the render-pass builder

2026-08-27 04:19:06 -04:00

VkSamplerManager.cpp

p5f fm: build Vulkan samplers from server-owned values

2026-09-19 22:27:43 -04:00

VkSamplerManager.h

p5f fm: build Vulkan samplers from server-owned values

2026-09-19 22:27:43 -04:00

VkTextureManager.cpp

[Merge] (P11): dev@c14283ee - scattered sub-image writes upload exactly their texels, Magma submits a frame's recording every 16384 draws with backpressure, and Magma grows descriptor pools geometrically and trims a quiet slot whole; the handle arm notes driver-side writes by handle and the wire arm splits recordings and keeps the trim's epoch peak across descriptor rewinds

2026-09-29 12:11:37 -04:00

VkTextureManager.h

[Merge] (P11): dev@c60639db - the Espryt image-bindable re-mint reads GPU levels back on the monolith arm too, partial writes into converted or reshaped levels upload only their region on every arm, Magma orders an upload after the recording's writes and queued clears, and Magma's eglSwapInterval reaches the swapchain

2026-09-29 06:15:56 -04:00

VkTextureSamplerManager.cpp

Merge branch 'dev' into Feat/Backend-Direct-Vulkan

2026-03-08 10:31:44 +08:00

VkTimerQueryManager.cpp

[Fix, Feat, Test] (MG_Util, MG_Backend, MG_Impl, MG_State): correct the log severity ordering and unwind the diagnostics it silenced

2026-08-13 02:02:49 -04:00

VkTimerQueryManager.h

[Feat] (MG_Impl, MG_Backend): GL_ARB_timer_query on both backends

2026-07-10 01:08:38 +00:00

VulkanRenderer.cpp

[Fix] (Magma, P8-SV): the wire arm's 3D native mip blit uses one layer with the depth in its z offsets, the depth/stencil mip decline gets its WireDeclineTally row (MipmapDepthStencilAspect), the depth shader mip refuses 1D/1D-array/3D view types before the chain grows, and glDispatchComputeIndirect is issued as vkCmdDispatchIndirect from the wire store (P8-D's barrier rule, wdsp counter, two named declines)

2026-09-30 03:44:03 -04:00

VulkanRenderer.h

[Fix] (Magma, P8-SV): the wire arm's 3D native mip blit uses one layer with the depth in its z offsets, the depth/stencil mip decline gets its WireDeclineTally row (MipmapDepthStencilAspect), the depth shader mip refuses 1D/1D-array/3D view types before the chain grows, and glDispatchComputeIndirect is issued as vkCmdDispatchIndirect from the wire store (P8-D's barrier rule, wdsp counter, two named declines)

2026-09-30 03:44:03 -04:00

WireColorBlit.frag

[MG_Backend, MG_IntegrationTest] (Disaggregated): rotate native Magma window blits through server-owned shaders

2026-09-20 03:06:26 -04:00

WireColorBlit.inc

[MG_Backend, MG_Test] (P7): the wire arm's shader colour blit samples an unscaled blit through its nearest sampler, so a 1:1 GL_LINEAR glBlitFramebuffer into the default framebuffer is an exact copy

2026-09-23 18:59:20 -04:00

WireColorBlit.vert

[MG_Backend, MG_IntegrationTest] (Disaggregated): rotate native Magma window blits through server-owned shaders

2026-09-20 03:06:26 -04:00

WireColorBlitFilter.h

[MG_Backend, MG_Test] (P7): the wire arm's shader colour blit samples an unscaled blit through its nearest sampler, so a 1:1 GL_LINEAR glBlitFramebuffer into the default framebuffer is an exact copy

2026-09-23 18:59:20 -04:00

WireColorBlitSpirv.h

[MG_Backend, MG_Test, MG_IntegrationTest, scripts, docs] (P7): the depth mip chain is baked, and every baked header in the tree now has to match its source

2026-09-22 16:37:54 -04:00

WireDeclines.def

[Fix] (Magma, P8-SV): the wire arm's 3D native mip blit uses one layer with the depth in its z offsets, the depth/stencil mip decline gets its WireDeclineTally row (MipmapDepthStencilAspect), the depth shader mip refuses 1D/1D-array/3D view types before the chain grows, and glDispatchComputeIndirect is issued as vkCmdDispatchIndirect from the wire store (P8-D's barrier rule, wdsp counter, two named declines)

2026-09-30 03:44:03 -04:00

WireDeclineTally.h

[MG_Backend] (P7): comment-only - the tally header names the macro that exists, and the def says the wire arm declines, not the draw

2026-09-22 21:28:02 -04:00

WireDepthMipmap.frag

[MG_Backend, MG_Test, MG_IntegrationTest, scripts, docs] (P7): the depth mip chain is baked, and every baked header in the tree now has to match its source

2026-09-22 16:37:54 -04:00

WireDepthMipmap.inc

[Fix] (Magma, P8-SV): the wire arm's 3D native mip blit uses one layer with the depth in its z offsets, the depth/stencil mip decline gets its WireDeclineTally row (MipmapDepthStencilAspect), the depth shader mip refuses 1D/1D-array/3D view types before the chain grows, and glDispatchComputeIndirect is issued as vkCmdDispatchIndirect from the wire store (P8-D's barrier rule, wdsp counter, two named declines)

2026-09-30 03:44:03 -04:00

WireDepthMipmap.vert

[MG_Backend, MG_Test, MG_IntegrationTest, scripts, docs] (P7): the depth mip chain is baked, and every baked header in the tree now has to match its source

2026-09-22 16:37:54 -04:00

WireDepthMipmapSpirv.h

[MG_Backend, MG_Test, MG_IntegrationTest, scripts, docs] (P7): the depth mip chain is baked, and every baked header in the tree now has to match its source

2026-09-22 16:37:54 -04:00

WireDepthResolveArm.h

[MG_Backend, MG_Test, MG_IntegrationTest, scripts] (P7): a private image placeholder is keyed by (shape, unit) and capped, and the depth-resolve identity is built by a tested helper

2026-09-23 17:45:57 -04:00

WireDepthResolveProbe.cpp

[MG_Backend, MG_IntegrationTest] (P7): a real-probe negative control proves the depth-resolve measurement can see a broken render-pass arm on the host

2026-09-23 15:20:17 -04:00

WireDepthResolveProbe.h

[MG_Backend, MG_IntegrationTest] (P7): a real-probe negative control proves the depth-resolve measurement can see a broken render-pass arm on the host

2026-09-23 15:20:17 -04:00

WireDraw.inc

[Fix] (Magma, P8-SV): the wire arm's 3D native mip blit uses one layer with the depth in its z offsets, the depth/stencil mip decline gets its WireDeclineTally row (MipmapDepthStencilAspect), the depth shader mip refuses 1D/1D-array/3D view types before the chain grows, and glDispatchComputeIndirect is issued as vkCmdDispatchIndirect from the wire store (P8-D's barrier rule, wdsp counter, two named declines)

2026-09-30 03:44:03 -04:00

WireFramebuffer.inc

[Fix] (Magma, P8-SV): the wire arm's 3D native mip blit uses one layer with the depth in its z offsets, the depth/stencil mip decline gets its WireDeclineTally row (MipmapDepthStencilAspect), the depth shader mip refuses 1D/1D-array/3D view types before the chain grows, and glDispatchComputeIndirect is issued as vkCmdDispatchIndirect from the wire store (P8-D's barrier rule, wdsp counter, two named declines)

2026-09-30 03:44:03 -04:00

WireMultisampleDepthResolve.frag

[MG_Backend, MG_IntegrationTest, MG_Test] (P7): a multisample depth or stencil buffer resolves on a device with no resolve extension, and the sample-count shapes with no arm decline

2026-09-22 18:29:22 -04:00

WireMultisampleResolve.inc

[MG_Backend, MG_Test, MG_IntegrationTest, scripts] (P7): choose the multisample depth/stencil resolve arm by a device probe with a shader-arm control instead of the Qualcomm vendor id

2026-09-23 15:13:44 -04:00

WireMultisampleResolve.vert

[MG_Backend, MG_IntegrationTest, MG_Test] (P7): a multisample depth or stencil buffer resolves on a device with no resolve extension, and the sample-count shapes with no arm decline

2026-09-22 18:29:22 -04:00

WireMultisampleResolveSpirv.h

[MG_Backend, MG_IntegrationTest, MG_Test] (P7): a multisample depth or stencil buffer resolves on a device with no resolve extension, and the sample-count shapes with no arm decline

2026-09-22 18:29:22 -04:00

WireMultisampleStencilResolve.frag

[MG_Backend, MG_IntegrationTest, MG_Test] (P7): a multisample depth or stencil buffer resolves on a device with no resolve extension, and the sample-count shapes with no arm decline

2026-09-22 18:29:22 -04:00

WirePlaceholderImages.inc

[MG_Backend, MG_Test, MG_IntegrationTest, scripts] (P7): a private image placeholder is keyed by (shape, unit) and capped, and the depth-resolve identity is built by a tested helper

2026-09-23 17:45:57 -04:00

WirePlaceholderKey.h

[MG_Backend, MG_Test, MG_IntegrationTest, scripts] (P7): a private image placeholder is keyed by (shape, unit) and capped, and the depth-resolve identity is built by a tested helper

2026-09-23 17:45:57 -04:00

WireRenderPassCompatibility.h

[Magma] key wire pipelines by exact render-pass compatibility identities

2026-09-20 08:42:47 -04:00

WireTextureReadback.inc

[MG_Backend] (DirectVulkan): the shared depth/stencil packer's call site keeps the file's argument alignment

2026-09-20 21:37:14 -04:00